Displays, such as flat panel displays, e.g. liquid crystal displays (LCD), OLED displays, and electroluminescent displays, include a light emitting assembly having two panels provided with two kinds of field generating electrodes, such as pixel electrodes and a common electrode, and an electrically operable layer interposed therebetween. By varying the voltage between the field generating electrodes, the luminance of each pixel is varied. A color display receives N-bit red (R), N-bit green (G), and N-bit blue (B) data from an external graphic source. A signal controller of the display converts the format of the RGB data, and controls a driving unit, which outputs analogue grey voltages corresponding to the RGB data. The grey voltages are applied to the light emitting assembly.
The bit number N of the RGB data input to the signal controller is usually equal to the bit number of data capable of being processed at the driving unit. Currently, available flat panel displays usually process 8-bit data using driving units capable of processing 8-bit RGB data. However the costs thereof are high. There is also a desire to reduce the power consumption. Attempts have been made to design a more cost-effective and low power display by using driver units of a reduced bit number L, such as 6, and mapping the N RGB bits onto the L bits of driver input data. By doing this the image quality is deteriorated. As described in the published US patent application with Pub. No. US 2003/0184508, a method called frame rate control (FRC) has been developed for reconstructing, or virtualizing, as many greys as possible of the 2N originally available greys with only 2L greys available. The FRC has been performed by providing, for each frame, i.e. image data, to be displayed, a plurality of consecutive subframes, or intermediate frames, some pixels thereof having varying greys, such that an average taken over the plurality of subframes simulates, as closely as possible, the frame that would have been generated if all N bits had still been available. This has been done as follows.
The N bits of data are mapped to the L bits of data such that the L upper, or most significant, bits of the N bits are mapped to the L bits while using the remaining M lower, or least significant, bits (LSBs) for generating a sequence of 2M subframes. The M LSBs regulates the number of subframes where the mapped data represents a grey ‘A’ indicated by the L bits and the number of subframes where the mapped data represents the next higher grey ‘A+1’. Additionally, the FRC maps the N-bit data into a predetermined number of L-bit data respectively assigned to pixels in a group of the predetermined number of pixels such that the total number of pixels displaying the grey ‘A’ and the total number of pixels displaying the grey ‘A+1’ during a predetermined number of frames are regulated depending on the M LSBs. Due to the averaging effect in the human eye, additional greys between ‘A’ and ‘A+1’ can be displayed.
For example, assume that N=8, and L=6. thus, M=2. the 8-bit input data can represent 256 (28) different greys ranging from ‘0’ to ‘255’. The upper 6 bits of the input data representing the highest four greys are all equal to ‘111111’ when mapped to the L bits provided to the driver unit. Since there is no 6-bit number larger than ‘111111’ by one, the FRC cannot be applied to these data, and thus the input data representing any of those highest four greys will be represented by a single 6-bit data ‘111111’ for all the subframes. Then, each of red, green and blue colors has only 253 greys.
In accordance with US 2003/0184508 a full number of greys is obtained as follows. The N-bit input data is first up-converted to have a bit number P that is larger than the bit number N of the input data, and then the P bits of the up-converted data are mapped onto a bit number L that is lower than N by mapping the L most significant bits of the P bits onto the L bits and then performing the FRC according to the principle described above. For example, 8 bits are converted to 9 bits. The 6 most significant bits of the 9 bits are used as the 6 bits input to the driver unit. By adding a most significant bit of ‘0’ it is possible to represent all 256 greys. However since the LSBs are now three, i.e. M=3, this is to the prize of generating eight rather than four consecutive subframes. Further, the conversion of 8 bits to 9 bits and the processing of the 9 bits requires additional hardware. Since the ordinary frame rate typically is 60 Hz, in this prior art solution the frame rate is 8-fold, i.e. 480 Hz. The power consumption of an LCD is proportional to the frame rate, and thus the prior art solution providing 256 greys causes a power consumption increase by a factor eight.